1. Field of the Invention
The present invention relates to a timing signal generating apparatus for generating a timing signal on the basis of a program, a method of detecting any set error to the program for a timing signal, and a semiconductor device testing apparatus using such timing signal generating apparatus. More particularly, the present invention relates to a timing signal generating apparatus provided with a set error detecting means being capable of immediately detecting any description error that may exist in a preset program, a method of detecting any set error to the program for a timing signal, and a semiconductor device testing apparatus using such timing signal generating apparatus.
2. Description of the Related Art
A timing signal generating apparatus for generating a timing signal on the basis of a program is used in, for example, a semiconductor device testing apparatus for testing a semiconductor device. FIG. 11 shows an example of a conventional semiconductor device testing apparatus (hereinafter referred to as an IC tester) for testing a semiconductor integrated circuit element (hereinafter referred to as an IC) which is a typical example of a semiconductor device. This IC tester TES comprises, roughly speaking, a main controller 111, a pattern generator 112, a timing generator 113, a waveform formatter 114, a logical comparator 115, a driver group 116, an analog level comparator group 117, a failure analysis memory 118, a logical amplitude reference voltage source 121, a comparison reference voltage source 122, and a device power supply 123.
The main controller 111 is generally comprised of a computer system and mainly controls the pattern generator 112 and the timing generator 113 in accordance with a test program PM created by a user.
First of all, prior to starting an IC test, a set of various data is performed by the main controller 111. After those various data are set, the IC test is started. By supplying a test start command from the main controller 111 to the pattern generator 112, the pattern generator 112 starts to generate a pattern. Therefore, a time point when the pattern generator 112 starts to generate a pattern is a time point when the test is started. The pattern generator 112 supplies a test pattern data to the waveform formatter 114 in accordance with the test program. On the other hand, the timing generator 113 generates a timing signal (clock pulses) for controlling the operation timings of the waveform formatter 114, the logical comparator 115 and the like.
The waveform formatter 114 converts a test pattern data supplied from the pattern generator 112 to a test pattern signal having a real waveform. This test pattern signal is applied to an IC under test (generally referred to as a DUT) 119 via the driver group 116 for amplifying voltage of the test pattern signal to a waveform having an amplitude value set in the logical amplitude reference voltage source 121, and is stored in a memory of the IC under test 119.
On the other hand, a response signal read out from the IC under test 119 is compared by the a logical comparator 117 with the a reference voltage supplied from the comparison reference voltage source 122 to determine whether or not the response signal has a voltage of a predetermined logical level (a voltage of logical H (logical high) or a voltage of logical L (logical low)). The response signal determined to have the predetermined logical level is sent to the logical comparator 115, where the response signal is compared with an expected value pattern signal outputted from the pattern generator 112.
If the response signal is not equal to the expected value pattern signal, a memory cell having an address of the IC under test 119 from which the response signal was read out is determined to be in failure, and a failure signal indicating this is generated. Usually this failure signal is expressed by a logical "1" signal, and is stored in the failure analysis memory 118. A failure signal is generally stored in an address of the failure analysis memory 118 that is same as that of the IC under test 119.
On the contrary, if the response signal is equal to the expected value pattern signal, a memory cell having an address of the IC under test 119 from which the response signal was read out is determined to be normal, and a pass signal indicating this is generated. This pass signal is expressed by a logical "0" signal, and is not usually stored in the failure analysis memory 118.
When the test is completed, the failure signals stored in the failure analysis memory 118 are read out therefrom, then, for example, whether or not a relief of the failure memory cells of the tested IC 119 is possible is determined.
The timing generator 113 generates a timing signal (clock pulses) for defining a rising timing and a falling timing of the waveform of the test pattern signal to be applied to the IC under test 119, a timing signal (clock pulse) of a strobe pulse for defining a timing of a logical comparison between the response signal and the expected value pattern signal in the logical comparator 115, and the like.
The IC tester is constructed such that the timings and/or periods for generating those timing signals are described in a test program PM created by the user, and the test pattern signal is applied to the IC under test 119 at operation periods and timings intended by the user to operate the IC under test, and in addition, a test can be performed to see if the operation is normal.
Next, an outline of the timing generator 113 and the waveform formatter 114 will be described with reference to FIG. 12. FIG. 12 shows a schematic configuration of the waveform formatter and the timing generator for generating one channel test pattern signal. As illustrated, the waveform formatter 114 can be constituted by an S-R (set/reset) flip-flop FF, which can generate a test pattern signal TP rising at a predetermined timing T1 and falling at a predetermined timing T2 by supplying a set pulse P.sub.S to its set terminal S and by supplying a reset pulse P.sub.R to its reset terminal R.
Those set pulse P.sub.S and reset pulse P.sub.R are generated by a pair of clock generators 113A and 113B, respectively. Delay data DY.sub.S and DY.sub.R read out from a delay data memory 113C are supplied to those clock generators 113A and 113B, respectively, and a generation timings of the set pulse P.sub.S and the reset pulse P.sub.R are defined by the delay data DY.sub.S and DY.sub.R, respectively.
The delay data memory 113C is accessed by an address signal supplied from an address counter 113D. The address counter 113D generates, from the test starting time, an address signal the address of which is incremented by +1 in every test period TS.sub.RAT (refer to FIG. 13). Therefore, the delay data memory 113C is accessed, in every test period TS.sub.RAT during the test, by the address signal the address of which is incremented by +1 in the sequential order, and the delay data DY.sub.S and DY.sub.R set therein in advance are read out therefrom in every test period TS.sub.RAT. Those delay data DY.sub.S and DY.sub.R are set in the clock generators 113A and 113B, respectively, and the set pulse P.sub.S and the reset pulse P.sub.R are generated based on those delay data, respectively.
The above operation will be described with reference to FIG. 13. The clock generator 113A generates a set pulse P.sub.S shown in FIG. 13B at a timing delayed by the set delay data DY.sub.S1 from, for example, a rising timing of a rate clock RAT shown in FIG. 13A defining a test period TS.sub.RAT during the test. In addition, the clock generator 113A generates a reset pulse P.sub.R shown in FIG. 13C at a timing delayed by the set delay data DY.sub.R1 from a rising timing of the rate clock RAT. By the above operation, a test pattern signal TP shown in FIG. 13D having a pulse duration corresponding to a time difference T.sub.PW from a generation timing of the set pulse P.sub.S to a generation timing of the reset pulse P.sub.R is generated by the waveform formatter 114.
In such a way, the rising timing and the falling timing of the test pattern signal TP are defined, in every test period TS.sub.RAT, by the delay data DY.sub.S and DY.sub.R, respectively. For example, a test is performed to find how much the pulse duration of the test pattern signal TP can be made narrower for the normal operation of the IC under test, how much the generation time interval (the time difference from the generation timing of a reset pulse P.sub.R to a generation timing of a next set timing P.sub.S) between the test pattern signals can be made small for the normal operation of the IC under test, or the like.
FIG. 14 is a block diagram showing in detail an internal configuration of the clock generator 113A for generating a set pulse P.sub.S. Further, since an internal configuration of the clock generator 113B for generating a reset pulse P.sub.R is similar to that of the clock generator 113A, the configuration and the operation of the set side clock generator 113A will be described here.
The clock generator 113A comprises, dividing into large components, an integer delay giving device 10 for providing a delay time of an integer multiplied by one period of a reference clock REFCLK shown in FIG. 15A, the one period of the reference clock being used as a unit delay time, an odd delay giving device 20 provided at the output side of the integer delay giving device 10, and a summation processing device 30 provided at the input side of the integer delay giving device 10, a fixed value storage device 31 at the input side of the integer delay giving device 10, and a latch circuit 32 at the input side of the integer delay giving device 10. The odd delay giving device 20 provides a delay time smaller than one period of the reference clock REFCLK, and hence it provides a delay time of a residue which cannot be divided by one period of the reference clock REFCLK.
The integer delay giving device 10 comprises a down-counter 11 for decrementing (down-counting) an integer value VDAT supplied from the summation processing device 30, first and second latch circuits 12 and 13 connected in cascade for adjusting an output timing of an odd value MDAT supplied from the summation processing device 30, a third latch circuit 14 for latching therein an integer delay signal MT outputted from the down-counter 11, and an AND gate 15 for performing an AND operation of a delayed pulse MT' outputted from the third latch circuit 14 and an inverted pulse of the reference clock REFCLK.
The summation processing device 30 performs an operation process for dividing a delay data by a time duration of one period of the reference clock REFCLK, and for separating the division result into an integer quotient (hereinafter referred to as an integer value) and a residue (hereinafter referred to as odd value or fraction value). The summation processing device 30 sums a delay data DY.sub.S read out from the delay data memory 113C and a fixed value skew SKEW read out from the fixed value storage device 31, and divides the summed result by a time duration of one period of the reference clock REFCLK to obtain an integer value VDAT and an odd value MDAT. The obtained integer value VDAT is supplied to a data input terminal D of the down-counter 11, and the odd value MDAT is supplied to a data input terminal D of the first latch circuit 12.
The odd value MDAT is outputted to the odd delay giving device 20 via the first and second latch circuits 12 and 13 for timing adjustment in synchronism with a timing when the integer delay giving device 10 outputs a delay pulse P.sub.0 to the odd delay giving device 20.
The operations of the integer delay giving device 10 and the odd delay giving device 20 will be described in further detail with reference to FIG. 15. Further, as shown in FIG. 14, each of the delay data memory 113C, the down-counter 11, the latch circuit 32, and the first to the third latch circuits 12, 13 and 14 is driven by the reference clock REFCLK shown in FIG. 15A.
A period cycle signal LRAT which is a logical signal shown in FIG. 15B is directly supplied to an enable terminal E of the delay data memory 113C. Therefore, the delay data DY.sub.S1, DY.sub.S2, . . . are read out, as shown in FIG. 15D, from the delay data memory 113C in synchronism with the period cycle signal LRAT. FIG. 15C shows the content of the address supplied to an address terminal ADDRESS (ADR) of the delay data memory 113C. In the example of FIG. 15, there is shown a case that the delay data DY.sub.S1 is set to DY.sub.S1 =30 ns, the delay data DY.sub.S2 is set to DY.sub.S2 =7.5 ns, the fixed value SKEW is set to SKEW=12 ns.
The summation processing device 30 calculates, in a first test period TS1, 30 ns+12 ns=42 ns, and at the same time, divides the calculated result 42 ns by the period of the reference clock REFCLK (in the illustrated example, 8 ns) to obtain an integer value VDAT=5 (40 ns) and an odd value MDAT=2 (2 ns). The summation processing device 30 calculates, in a second test period TS2, 7.5 ns+12 ns=19.5 ns, and divides the calculated result 19.5 ns by 8 ns to obtain an integer value VDAT=2 (16 ns) and an odd value MDAT=3.5 (3.5 ns).
The period cycle signal LRAT is also supplied to a data input terminal D of the latch circuit 32. This latch circuit 32 delays, as shown in FIG. 15H, the supplied period cycle signal LRAT to a timing when the next reference clock REFCLK is supplied thereto to supply the delayed period cycle signal LRAT to a load terminal LD of the down-counter 11 and to an enable terminal E of the first latch circuit 12. As a result, the integer value VDAT=5 from the summation processing device 30 is loaded in the down-counter 11 at a timing delayed by an amount of one period of the reference clock REFCLK. In addition, the first latch circuit 12 latches therein, at the same timing as this timing, the odd value MDAT=2 from the summation processing device 30. The integer value VDAT loaded in the down-counter 11 and the odd value latched in the first latch circuit 12 are updated, when a next period cycle signal LRAT is supplied thereto, to an integer value and an odd value of the next test period.
The down-counter 11 down-counts by 1 (decrements the integer value by 1), as shown in FIG. 15I, the loaded integer value VDAT at every, for example, rising timing of the reference clock REFCLK. When the loaded integer value VDAT becomes "0", the down-counter 11 stops the count operation and outputs an integer delay signal MT of logical H shown in upper side of FIG. 15J.
The integer delay signal MT of logical H outputted from the down-counter 11 is supplied to an enable terminal E of the second latch circuit 13 and a data input terminal D of the third latch circuit 14. As a result, the second latch circuit 13 acquires the odd value MDAT=2 latched in the first latch circuit 12 from its data input terminal D and supplies the acquired odd value MDAT to a control input terminal of the odd delay giving device 20 to set the delay time of the odd delay giving device 20 to the odd value=2 (2 ns).
At the same time, the third latch circuit 14 acquires the integer delay signal MT and inputs the integer delay signal MT to one input terminal of the AND gate 15 as a delay pulse MT' of logical H shown in lower side of FIG. 15J. Since an inverted pulse of the reference clock REFCLK inverted by the inverter IN is applied to the other input terminal of the AND gate 15, the AND gate 15 outputs a pulse P.sub.0 shown in FIG. 15K during a time when the reference clock REFCLK is logical L. This pulse P.sub.0 is inputted to the odd delay giving device 20.
Since the odd delay giving device 20 has the amount of delay 2 ns already set therein by the output signal MDAT of the second latch circuit 13, the odd delay giving device 20 outputs a set pulse P.sub.S1 which is further delayed by 2 ns from the pulse P.sub.0. Since, in the next test period TS2, the odd value MDAT is 3.5 ns, the amount of delay of the odd delay giving device 20 is set to 3.5 ns. Therefore, in the next test period TS2, the odd delay giving device 20 outputs a set pulse P.sub.S2 which is further delayed by 3.5 ns from the pulse P.sub.0.
In such away, a set pulse P.sub.S is generated by the clock generator 113A constructed as mentioned above, and a reset pulse P.sub.R is generated by the other clock generator 113B. It could be easily understood that the waveform formatter 114 is driven by the set pulse P.sub.S and the reset pulse P.sub.R to generate a test pattern signal TP.
In the aforementioned description of the operation, it is assumed that each of the delay data DY.sub.S and DY.sub.R read out from the delay data memory 113C and inputted to the summation processing device 30 has a proper value. However, in practice, the delay data stored in the delay data memory 113C is a delay data which is read into the main controller 111 shown in FIG. 11 and transferred therefrom to the delay data memory 113C. Namely, the delay data stored in the delay data memory 113C is, tracing back to the origin, the delay data that has been written by the user in the test program PM. Therefore, there is possibly a case that the user has described an erroneous (improper) set value in the test program.
For example, like a set state that a time duration from a generation timing of a set pulse P.sub.S to a generation timing of a reset pulse P.sub.R (set-reset time duration or time width) is too short in one test period or a set state that a time duration from a generation timing of a reset pulse P.sub.R to a generation timing of a next set pulse P.sub.S (reset-set time duration or time width) is too short, or the like, in the case that the user has erroneously described those time durations, the IC tester may not normally operate. In such a case that a test is performed in the state of a set error, there occurs an erroneous operation that a normal IC is determined to be a failure IC. For this reason, in the IC tester using the conventional timing generating apparatus, there is a serious drawback that a failure occurring rate becomes high and an analysis of the cause takes a long time.